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| DISCRETE SEMICONDUCTORS DATA SHEET BGB101 0 dBm Bluetooth radio module Preliminary specification 2003 Aug 05 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module FEATURES * Plug-and-play Bluetooth class 2 radio module, needs only external antenna and reference clock * Low current consumption from 2.8 V supply * Wide operating temperature range (-30 to +85 C) * Small dimensions (10.5 x 8.5 x 1.8 mm) * Fully compliant to Bluetooth Radio Specification v1.1 * High sensitivity (typical -82 dBm) * Advanced DC offset compensation for improved reception quality * RSSI with high dynamic range * Simple interfacing to baseband controller, control by 3-wire serial bus * Internal shielding for better EMI (Electro Magnetic Interference) immunity. APPLICATIONS Bluetooth transceivers in: * Cellular phones * Laptop computers * Personal digital assistants * Consumer applications. BGB101 DESCRIPTION The BGB101 Bluetooth radio module is a short-range radio transceiver for wireless links operating in the globally available ISM band, between 2402 and 2480 MHz. It is composed of a fully integrated, state-of-the-art near-zero-IF transceiver chip, an antenna filter for out-of-band blocking performance, a TX/RX switch, TX and RX balans, the VCO resonator and a basic amount of supply decoupling. The device is a "Plug-and Play" module that needs no external components for proper operation. Robust design allows for untrimmed components, giving a cost-optimized solution. Demodulation is done in open-loop mode to reduce the effects of reference frequency breakthrough on reception quality. An advanced offset compensation circuit compensates for VCO drift and RF frequency errors during open-loop demodulation, under control by the baseband processor. The circuit is integrated on a ceramic substrate. It is connected to the main PCB through a LGA (Land Grid Array). The RF port has a normalized 50 impedance and can be connected directly to an external antenna, with a 50 transmission line. The interfacing to the baseband processor is very simple, which leads to a low-power solution. Control of the module operating mode is done through a 3-wire serial bus and one additional control signal. TX and RX data I/O lines are analogue-mode interfaces. A high-dynamic range RSSI output allows near-instantaneous assessment of radio link quality. Frequency selection is done internally by a conventional synthesizer. It is controlled by the same serial 3-wire bus. The synthesizer accepts reference frequencies of 12 and 13. This reference frequency should be supplied by an external source. This can be a dedicated (temperature compensated) crystal oscillator or be part of the baseband controller. The circuit is designed to operate from 3.0 V nominal supplies. Separate ground connections are provided for reduced parasitic coupling between different stages of the circuit. There is a basic amount of RF supply decoupling incorporated into the circuit. The envelope is a leadless SOT750A package with a plastic cap. CAUTION This device is sensitive to electrostatic discharge (ESD). Therefore care should be taken during transport and handling. 2003 Aug 05 2 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module PINNING PIN 1,2,3,4,5,6, 7,8,9,10,12, 15,18,25,26 ,28, 29 11 13 14 16 17 19 20 21 22 23 24 27 NAME GND DESCRIPTION ground (all ground pins should be short-circuited externally) BGB101 VS1 VS2 RSSI supply voltage ( for VCO, buffer and synthesizer) supply voltage (TX) received signal strength indicator T_GFSK transmit data input REFCLK reference clock input R_DATA received data output S_DATA S_EN S_CLK VS3 ANT 3-wire bus data input 3-wire bus enable input 3-wire bus clock input supply voltage (RX) antenna input/output TOP VIEW Dimensions in mm Pin 29 represents the inner 5 x 7 = 35 LGA pads DCXCTR DC extractor control signal Fig.1 Simplified outline (preliminary footprint) BLOCK DIAGRAM BGB101 PLL loop filter RF IC :2 _GFSK REFCLK Regulator Control logic Synthesizer S_EN S_CLK S_DATA Demod Autocal Channel Filter Tx balun + filter DC extractor Vs1 Vs2/Vs3 GND R_DATA DCXCTR RSSI Supply decoupling Rx balun + filter Tx/Rx switch Band pass filter ANT Fig.2 Block diagram. 2003 Aug 05 3 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module QUICK REFERENCE DATA VS = 3.0 V; Tamb = 25 C; unless otherwise specified. SYMBOL VS1, VS2,VS3 PARAMETER nominal supply voltage during RX guard space during demodulation during TX guard space during transmission in power-down mode Sens Pout f0 fref Tamb receiver sensitivity output power RF frequency reference input frequency operating ambient temperature BER 0.1 % and PER < 0.5 % under standard conditions at nominal settings CONDITIONS - - - - - - -2 2402 12 -30 MIN. 2.65 TYP. 2.8 15 40 15 33 10 -82 1 - - - BGB101 MAX. 3.4 - 48 - 40 30 -75 +4 2480 26 +85 UNIT V mA mA mA mA A dBm dBm MHz MHz C IS1 + IS2 + IS3 total supply current FUNCTIONAL DESCRIPTION Control The BGB101 Bluetooth Radio Module is controlled by a baseband processor via the serial 3-wire bus. These 3 wires are data (S_DATA), clock (S_CLK) and enable (S_EN). Data sent to the device is loaded in bursts framed by S_EN. Data and clock (S_DATA and S_CLK) signals are ignored until S_EN goes low. The programmed information is read directly into the internal registers when S_EN goes high. S_DATA and S_EN should be stable around the rising edges of S_CLK. There are internal pull-down resistors on all these three pins. Only the last 32 bits serially clocked into the device are retained within the register. Additional (leading) bits are ignored, and no check is made on the number of bits received. The data format is shown in table 1. The first data bit entered is b31, the last one b0. The S_EN high-to-low transition also controls the opening of the PLL. A short S_EN high pulse at the end of a time slot, either TX or RX, serves to reset and power-down the IC. This can be omitted, at the cost of extra power consumption. In addition to the 3-wire serial bus, there is one control signal used for accurate timing of functions within the IC, under control by the baseband processor. This is the DCXCTR, to control (in RX mode) the three subsequent operating modes of the DC compensation circuit: coarse offset estimation during the early part of the Access Code, accurate offset estimation during the Barker sequence and the trailer, retention of the offset information during the payload. In addition DCXCTR (in TX mode) is used to switch the output amplifier on independently from the S_EN pulse. This makes it possible to switch the output amplifier on while the PLL is still active, thus compensating for the frequency jump (Initial Carrier Frequency Offset) this might otherwise cause. Transmit mode The BGB101 Bluetooth Radio Module contains a fully integrated transmitter function. The RF channel frequency is selected in a conventional synthesizer, which is controlled via the serial 3-wire bus. The VCO is directly modulated by the signal present on the T_GFSK connection. The Gaussian filtering should therefore be performed externally. The DC bias voltage for this pin should already be present during the S_EN programming pulse, so that the PLL can correct for possible frequency errors that might otherwise occur. Also in RX mode, this pin should be connected to a well-defined and stable DC voltage. The fully integrated VCO operates at double the Bluetooth frequency. The VCO includes an on-chip regulator which minimizes frequency errors due to VS variations. This leads to a lower component cost. A carefully designed PLL loop filter keeps frequency drift during open-loop modulation down to a very low value. 2003 Aug 05 4 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module BGB101 The output stage of the transmit chain active part is balanced, for reduced spurious emissions (EMC). It is connected through a balun (balanced-to-unbalanced) circuit to the TX/RX switch. This switch is controlled by internal logic circuits in the active die. The balun circuit has built-in selectivity, to further reduce out-of-band spurious emissions. The output amplifier of the IC is switched on by pulling the DCXCTR control line high. This can be done before the S_EN line goes low. In this mode, the PLL compensates for the frequency jump (pulling) that might otherwise be caused by switching the output amplifier on when the PLL would already have been de-activated. The DCXCTR line should be kept high during the entire TX slot. The output power level is programmable with a dynamic range of approximately 19 dB with a maximum step size of 4 dB. In this way, a simple power amplifier can be added in the application with power control implemented by reducing the pre-amplifier gain. Receive mode Also the receiver functionality is fully integrated. It is a near-zero-IF (1 MHz) architecture with active image rejection. The integrated channel filters use a build-in auto calibration scheme, providing an excellent sensitivity over a wide temperature range. The sensitive RX input of the active die is a balanced configuration, in order to reduce unwanted (spurious) responses. The balun structure to convert from unbalanced to balanced signals has built-in selectivity. This suppresses GSM-900 frequencies by more than 40 dB. For better immunity to DCS, DECT, GSM-1800 and W_CDMA signals, an extra band-pass filter has been included. The synthesizer PLL may be switched off during demodulation. This reduces the effects that reference frequency breakthrough may have on receiver sensitivity and adjacent channel selectivity, and also reduces the power consumption. The demodulator contains an advanced DC offset compensation circuit. This reduces the effects of frequency mismatch between (remote) transmitter and receiver. These may be caused by differences in reference frequency, but also by frequency drift during open-loop modulation and demodulation. Because the VCO is directly modulated by the signal present at the T_GFSK pin, this pin should be connected to a well-defined and stable DC bias voltage, also when in RX mode. Moreover, this bias voltage should already be present during the S_EN programming pulse. In this way, the PLL can correct for possible frequency offsets that might otherwise occur. The demodulated RF signal is compared against a reference (slicer) value and then output. This reference voltage is derived from the demodulated output signal itself, by the DC extractor circuit. It operates in three subsequent phases, controlled by the DCXCTR signal: * In the first phase, during the preamble and the early part of the Access Code, a Min/Max detector provides a crude but fast estimate of the required DC voltage. The DCXCTR line should be low during this phase. * When the DCXCTR line is pulled high, this crude estimate is used as an initial guess for an integrator circuit that provides an accurate estimate of the required DC voltage. This is the second phase. The DC value obtained is derived from the Barker sequence and the trailer, which together make up the final 10 bits of the Access Code. The DCXCTR line should be pulled high 20 s before the trailer sequence is expected to end (there is a 10 s timing uncertainty between the expected and the actual end of the trailer sequence). * Exactly at the end of the trailer, the DCXCTR must be pulled low again. The device now enters the third phase, during which the estimate of the offset voltage that was obtained during phases one and two is retained. A small and slow variation to compensate carrier frequency drift can still be tracked. An RSSI output with a high dynamic range of more than 50 dB provides near-instantaneous information on the quality of the signal received. Due to the IF frequency at 1 MHz, in RX mode the VCO frequency should be 1 MHz higher than the channel frequency. This should be taken care of by the baseband controller. Power-down mode In Power-down mode, current consumption is reduced to 5 A (typical). The 3-wire bus inputs present a high-ohmic resistance to ground. 2003 Aug 05 5 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module Table 1 Bit allocation REGISTER BIT ALLOCATION(1) Data field FIRST IN b31 (2) BGB101 b30 (2) b29 (2) b28 (2) b27 (2) b26 (2) b25 (2) b24 (2) b23 (2) b22 (2) b21 (2) b20 (2) b19 (3) b18 (4) b17 (2) b16 (2) see below 0 LAST IN 0 0 0 0 0 tbd tbd tbd tbd tbd tbd tbd tbd 0 0 see b15 b14 (2) above 0 Notes ref1 (7) b13 ref0 (7) b12 b11 b10 b9 b8 trx (9) (10) b7 to b0 (6) main divider programming (11) pwr2 pwr1 pwr0 pll (8) (8) (8) 1. In normal operation, 32 bits are programmed into the register. 2. bits b31 to b20 and b17 to b15 are test bits and must always be programmed as described in table 1. 3. Bit b19 defines the transmit rampup mode (see Table 6) 4. Bit b18 defines the dc extraction mode (see Table 5). 5. Bit b7 is the MSB of the frequency control word composed of (b7, b6, b5, b4, b3, b2, b1 and b0). 6. ref: bits `ref1' and `ref0' define the reference frequency (see Table 3). 7. pwr: bits, `pwr2', `pwr1' and `pwr0' define the the typical output power (see Table 4). 8. pll: bit `pll' = 1 forces the synthesizer PLL to remain on during the entire (TX or RX) slot. 9. trx: bit `trx' = 1 forces the IC into RX mode. 10. The RF frequency is equal to 2304 + d[b7:b0] (see Table 2). Table 2 b7 Channel frequency programming examples b6 b5 b4 b3 b2 b1 b0 MAIN DIVIDER RATIO 2304 + n 0 0 0 0 1 1 0 0 0 1 0 1 2402 2403 2480 2481 SYNTHESIZED FREQUENCY (MHz) 1.0 x (2304 +n) 2402 2403 2480 2481 TX channel 1 RX channel 1 TX channel 2 RX channel 78 TX channel 79 RX channel 79 CHANNEL FREQUENCY Binary equivalent of n 0 0 1 1 Table 3 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 Reference frequency programming b14 0 1 b13 0 0 REFERENCE DIVIDER RATIO 12 13 REFERENCE INPUT FREQUENCY 12 MHz 13 MHz 2003 Aug 05 6 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module Table 4 Typical output programming b12 0 0 0 0 1 1 1 1 Table 5 b11 0 0 1 1 0 0 1 1 b10 0 1 0 1 0 1 0 1 BGB101 TX OUTPUT POWER (TYPICAL) -12 dBm -9 dBm -6 dBm -3 dBm 0 dBm +3 dBm +4 dBm +5 dBm DC extraction mode programming b18 0 1 DC EXTRACTION TYPE Mode 1 (min/max - Medium RC - Slow RC) Mode 2 (min/max - Slow RC) Table 6 b19 0 1 Transmit ramp-up mode (see figure 3) RISING EDGE S_EN RISING EDGE DCXCTR Pre-amplifier on - Amplifier on Pre-amplifier on FALING EDGE DCXCTR Tx/Rx switch in TX Amplifier on and Tx/Rx switch in TX FALING EDGE S_EN - - 2003 Aug 05 7 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER input control pin voltage GND Pi max Tstg Tj difference in ground supply voltage between ground pins maximum input power storage temperature junction temperature CONDITIONS MIN. -0.3 -0.3 - - -40 - VS 0.01 +4 +85 150 MAX. 3.6 BGB101 UNIT V V V dBm C C VS1, VS2, VS3 supply voltage THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient VALUE 30 UNIT K/W SPURIOUS EMISSIONS The conducted and radiated out-of-band spurious emissions in all operating modes are fully compliant with the Regulatory Requirement FCC Part 15.247,C and ETS300328 (subclause 5.2.4.). ESD PRECAUTIONS Inputs and outputs are protected against electrostatic discharge (ESD) during handling and mounting. A human-body model (HBM) and a machine model (MM) are used for ESD susceptibility testing. All pins withstands the following threshold voltages: PARAMETER ESD threshold voltage METHOD HBM (JESD22-A114-B) MM (JESD22-A115-A) VALUE 3500 V 300 V CLASS 2 2 2003 Aug 05 8 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module BGB101 CHARACTERISTICS VCC = 2.8 V;Tamb = 25 C; fdev = 160 kHz; unless otherwise specified. Characteristics for which only a typical value is given are not tested. SYMBOL Supply VS1, VS2, VS3 nominal supply voltage IS1 + IS2 + IS3 total supply current during RX guard space during RX (PLL off) during TX guard space during TX (PLL off) power-down mode Frequency selection fref fref Vref(min) Ri Ci f1 slot f3, 5 slots ICFT tPLL fRF kMOD Po Po min 111 Po 1 MHz initial carrier frequency tolerance PLL settling time reference input frequency reference frequency inaccuracy sinusoidal input signal level input resistance (real part of the input impedance) input capacitance (imaginary part of the input impedance) carrier drift RMS value at 13MHz at 13MHz over 1 TX slot; note 5 over 3, 5 TX slots (DM3, DH3, DM5, DH5 packets); note 5 note 5 across entire band; note 5 -tbd 250 - - -25 -40 -75 - 2402 - -2 +1 - 12,13 - - 2 2.5 0 0 0 150 - 1 1 - - tbd 500 - - 25 40 75 200 MHz ppm mV k pF kHz kHz kHz s MHz MHz/V dBm dBm dBc 2.65 - - - - - 2.8 15 40 15 33 5 3.4 - 48 - 40 30 V mA mA mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Transmitter performance RF frequency VCO modulation gain output power minimum output power adjacent channel output power over full temperature and supply range from T_GFSK (pad 3) to antenna (pad 21): note 2 bits b12,b11, b10 =1, 0, 1; note 5 bits b12,b11, b10 =1, 1, 1 at 1 MHz offset; measured in 100 kHz bandwidth; referred to wanted channel; note 5 note 5 and note 6 note 5 and note 6 normalized to Zo = 50 2480 - 4 - -20 fdev BW20dB VSWR H1, VCO frequency deviation 1111000 bit pattern 20 dB bandwidth voltage standing wave ratio VCO frequency feedtrough 140 - - - - 1.5 tbd 175 1 - tbd kHz MHz dBc referred to wanted output level; - fRF = 2450 MHz; fVCO = 4900 MHz; note 1; note 5 2003 Aug 05 9 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module BGB101 SYMBOL PARAMETER out of band spurious emissions (conducted) CONDITIONS 30 MHz to 1 GHz; note 5 1 GHz to 12.75 GHz; note 5 1.8 GHz to 1.9 GHz; note 5 5.15 GHz to 5.3 GHz; note 5 MIN. - - - - - - - TYP. - - - - -82 -80 -80 MAX. -36 -30 -47 -47 -75 -70 -75 UNIT dBm dBm dBm dBm Receiver performance SENS sensitivity for BER 0.1 % and PER 0.5 %; note 7 without carrier offset with dirty transmitter as specified in [1]; note 5 with dirty transmitter as specified in [1] at nominal test conditions Pi max VSWR fRF VRSSI Ton IM3 maximum input power in one channel voltage standing wave ratio RF input frequency RSSI voltage (monotonic over range -86 dBm to -36 dBm) BER < 0.1 %; note 5 normalized to Zo = 50 over full temperature and supply range Pin = -86 dBm Pin = -36 dBm dBm dBm dBm -20 - 2402 - - - 28 0 1.5 - 0.2 1.3 - - - - 2480 - - 50 - dBm MHz V V s dBc wake up time from the power up No external capacitor on the signal to correct RSSI output RSSI pin; Rload > tbf k intermodulation rejection wanted signal -64 dBm; Interferers 5 and 10 channels away; BER < 0.1 % wanted signal -60dBm; BER < 0.1 % wanted signal -60dBm; BER < 0.1 % wanted signal -60dBm; BER < 0.1 % wanted signal -60dBm; BER < 0.1 % wanted signal -67dBm; BER < 0.1 % wanted signal -67dBm; BER < 0.1 %; N+3 is a special case, see above RCO RC/I 1MHz RC/I -2MHz RC/I Image RC/I Image 1MHz co-channel rejection adjacent channel rejection ( 1 MHz) bi-adjacent channel rejection (N-2) rejection at image frequency (N+2) rejection at image-adjacent frequency (N+3) in-band interference rejection ratio, three or more channels away - - - - - - -11 3 33 11 27 43 - - - - - - dBc dBc dBc dBc dBc dBc RC/I 3MHz 2003 Aug 05 10 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module BGB101 SYMBOL PARAMETER out of band blocking (see also figure CONDITIONS wanted signal -67dBm; CW interferer level range 30 MHz to 2 GHz range 2 GHz to 2400 MHz range 2500 MHz to 3 GHz range 3 GHz to 12.75 GHz MIN. TYP. MAX. UNIT 0 -27 -27 0 - - - - - - - - - - dBm dBm dBm dBm dBm wanted signal -67dBm; GSM +20 modulated signal between 880 and 915 MHz (GSM-900 uplink) wanted signal -67dBm; GSM modulated signal between 1785 and 1800 MHz (GSM-1800 uplink) spurious emissions FTLOrf LO to RF feedthrough 30 MHz to 1 GHz; note 5 1 GHz to 12.75 GHz; note 5 measured at 2450MHz +20 - - dBm - - - 1.4 -0.3 -5 - 1 1.6 -0.3 - - - - - tbd tbd tbd - - - - - 1.7 - tbd 10 tbd tbd tbd -36 -30 -47 VS +0.4 +5 5 - 1.8 +0.4 - 30 - - - dBc dBc dBc Interface (logic) inputs and outputs; pins S_DATA, S_CLK, S_EN, DCXCTR, T_EN, R_DATA, T_GFSK VIH VIL Ibias fS_CLKmax tS_ENmin VOH VOL RR_DATA, load CR_DATA, load VT_GFSK,DC RT_GFSK,in CT_GSFK, in Notes 1. The actual VCO frequency is double the programmed frequency. It is divided by 2 internally. 2. T_GFSK is DC coupled. The DC voltage must be supplied by the baseband processor. 3. VIH should never exceed 3.6V. 4. See detailed timing information. 5. Over full temperature and supply voltage range. 6. In combination with the BlueBerry Baseband processor. 7. Packet Error Rate (PER): lost Packets due to access code or Packet-header failure. HIGH-level input voltage LOW-level input voltage input bias current minimum S_EN pulse duration HIGH-level output voltage LOW-level output voltage real part of the R_DATA load admittance imaginary part of the R_DATA load admittance T_GFSK DC voltage real part of the T_GFSK input admittance imaginary part of the T_GFSK input admittance HIGH or LOW level to switch off the module: note 3 for R_DATA output for R_DATA output at 500 kHz at 500 kHz note 2 at 500 kHz at 500 kHz maximum 3-wire bus frequency note 4 note 3 V V A MHz s V V pF V pF 2003 Aug 05 11 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module BGB101 Measured Blocking performance BGB101/BGB121, Pwanted = -67 dBm. 25 20 15 Measured BT spec Power level of interferer (dBm) 10 5 0 -5 -10 Note that the interferer maximum power level that could be generated in the test system was limited to +19 dBm. -15 -20 -25 -30 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 Interference Frequency (MHz) Fig.3 Typical out-of-band blocking performance BGB101. TIMING DIAGRAMS S_DATA S_CLK S_EN 32 clock cycles t3 31 30 29 210 3-wire serial bus timing TX packet S_CLK/DATA REFCLK t1 t2 t1 RX packet t2 S_EN T_GFSK t3 t4 t7 t11 t9 t3 t4 t8 t9 t10 R_DATA t12 DCXCTR t5 t6 t13 t14 Fig.4 Timing diagram. 2003 Aug 05 12 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module Timing Parameters BGB101 PARAMETER t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Notes DESCRIPTION S_DATA last bit to REFCLK enable S_EN falling edge to REFCLK disable S_DATA last bit to S_EN rising edge S_EN width DCXCTR rising edge before S_EN falling edge DCXCTR falling edge before S_EN falling edge T_GFSK last bit to S_EN pulse start R_DATA last bit to S_EN pulse start S_EN pulse width S_DATA last bit to T_GFSK DC bias S_EN falling edge to T_GFSK first data bit S_EN falling edge to R_DATA earliest data bit S_EN falling edge to DCXCTR high DCXCTR width (in RX mode) CONDITIONS - MIN. 0.1 0.1 TYP. - 2 - 185 60 55 2 2 2 - 2 20 tbd tbd UNIT s s s s s s s s s s s s s s note 1 note 2 note 2 180 - - - - note 3 note 4 - 0.1 - 15 - note 5 - 1. The S_EN signal going high switches the synthesiser on if preceded by S_DATA / S_CLK activity; the S_EN signal going low disables the synthesizer in order to perform open-loop modulation or demodulation. Simultaneously, it enables the receiver chain in RX mode. The length of the S_EN signal should be long enough for the synthesizer loop to settle. 2. The DCXCTR signal in TX mode serves to switch on the TX output inside the module (see also table 6). It should go high a sufficiently long time before the synthesizer loop is disabled ( by bringing the S_EN signal low) in order to allow the synthesizer loop to resettle. Doing this brings about a considerable reduction in Initial Carrier Frequency Tolerance and can give a clear improvement in link set-up time. 3. A single short S_EN pulse (without preceding S_DATA / S_CLK activity) serves to power-down the IC. It may be omitted at the cost of increased power consumption. Any subsequent S_EN pulse without preceding S_DATA / S_CLK activity toggles between power-up and power-down states, but brings the module into an undefined power-up state. This mode should be avoided. 4. Because the VCO is directly modulated by the T_GFSK signal, the DC level on this pin should be present early on during the synthesizer settling phase. Also in RX mode, there should be a well-defined and stable DC voltage on this pin. 5. The DCXCTR signal (in RX mode) should go low at the actual end of the trailer sequence. The timing for this transition should be directly derived from the Access Code detection algorithm inside the baseband processor. REFERENCES [1] Bluetooth test specification - RF, 20001-07-02, rev. 0.91, 20.B.353/0.91 2003 Aug 05 13 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module SOLDERING The indicated temperatures are those at the solder interfaces. Advised solder types are types with a liquidus less than or equal to 210 C. Solder dots or solder prints must be large enough to wet the contact areas. Soldering can be carried out using a conveyor oven, a hot air oven, an infrared oven or a combination of these ovens. A double reflow process is permitted. Hand soldering is not recommended because of the nature of the contacts. The maximum allowed temperature is 250 C for a maximum of 5 seconds. The maximum ramp-up is 10 C per second. The maximum cool-down is 5 C per second. Cleaning The following fluids may be used for cleaning: * Alcohol * Bio-Act (Terpene Hydrocarbon) * Acetone. Ultrasonic cleaning should not be used since this can cause serious damage to the product. Packing 0 0 1 2 3 4 100 handbook, halfpage BGB101 300 MGM159 T (C) 200 t (min) 5 Fig.6 Recommended reflow temperature profile. An extended packing / SMD specification can be found in document SC-18 "Discrete Semiconductor Packages". . The module is compliant with moisture sensitivity level 1. 2003 Aug 05 14 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module PACKAGE OUTLINE BGB101 1 2 3 4 5 6 7 8 9 28 27 26 25 24 10 11 12 13 14 23 22 21 20 19 18 17 16 15 2003 Aug 05 15 Philips Semiconductors Preliminary specification 0 dBm Bluetooth radio module DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION BGB101 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Aug 05 16 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands budgetnum/ed/pp17 Date of release: 2003 Aug 05 Document order number: 9397 750 12019 |
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